Configuring a PLA to "personalize" sequential and latching operations is used in the digital circuit art to reduce component count and to provide flexibility.
One example is shown in "Programmable Flip-Flop," J. E. Gersbach, IBM Technical Disclosure Bulletin, Vol. 18, No. 5, Oct. 1975, pp. 1323-1324. Although directed to teaching enhancements of PLA circuits by inserting a two-bit decoder between the PLA's OR array output and the controlled output register, it is typical of the prior art programming of latches using single level PLA's. A somewhat similar arrangement is shown in "PLA Having OR-Array Bit Partitioning," L. D. Whitley, IBM Technical Disclosure Bulletin, Vol. 24, No. 6, Nov. 1981, pp. 2747-2748.
U.S. Pat. No. 3,993,919 shows a PLA chip with latches included on the chip and represents a typical prior art approach using a single PLA comprising an AND array and an OR array with feedback coupling from the latch.
The cited prior art possesses limitations that result from the use of a single PLA.